The following invention relates generally to signal transmission in Very Large Scale Integration/Ultra Large Scale Integration (VLSI/ULSI) systems and specifically to an efficient process for evaluation of electrical digital signal transmission properties and performance optimization in VLSI/ULSI chip design.
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A typical problem in high performance digital circuit implementation is maintaining a sharp signal transition rate (or slew rate). A signal slew rate is defined as the rate of change of voltage at a given point (dv/dt). The signal slew is defined as the time it takes a signal at any given point to transition from one digital state (up or down level) to the opposite digital state (down or up level) respectively. Since the dv/dt of a signal is not constant (is non linear) it is customary to define a signal slew between two fixed voltage points which are within the extreme digital up and down level states, i.e. 10% to 90% points.
A circuit is defined as a collection of transistors arranged in such a way that the output signal is some function xe2x80x98fxe2x80x99 of the one or more input signals (output=f(input)). In a digital circuit the function xe2x80x98fxe2x80x99 is typically a Boolean relationship.
The propagation delay through a digital circuit is defined as the time required to achieve a stable output on the circuit once one or more of the inputs have changed states. The propagation delay is typically measured at some reference voltage point midway between the up and down levels. Some of the factors that affect the propagation delay through a circuit are: the physical geometries of the devices in the circuit, the output load on the circuit and the input signal slew rate.
The physical connection between two or more digital circuits is called a net. The net is typically implemented as one or more conducting wire segments. The driver of the net is the circuit which has its output connected to the net and typically has the capacity to electrically charge and discharge the net thus changing the electrical potential (or voltage). The receiver(s) of the net is the circuit which has one or more of its inputs connected to the net. There are typically one or more receivers on a net.
In a synchronous digital sate machine (semiconductor chip) there are numerous memory elements. The memory elements are also referred to as latches. Each latch is a circuit comprising many transistor devices which are used to store a binary state (high or low value). Synchronous clocks activate the latches at specific frequencies to reevaluate to new states. The state changes are a function of the Boolean logic circuit and net connections that are implemented between latches. The performance of the chip is measured as the propagation delay through a path of circuits and nets from one latch to a receiving latch. The slack on a given net can be derived from the propagation delay and required arrival time (to support a specific clock frequency). A positive slack indicates that the propagation delay through a path is smaller than the inverse of the clock frequency and there is some delay margin. A negative slack indicates that propagation delay through a path is larger than the inverse of the clock frequency and the system will not operate properly as a synchronous digital state machine since the wrong state may be captured.
A poor signal slew rate has several detrimental effects which impact the overall performance and electrical integrity of the digital circuit. The performance of a digital circuit is degraded by a poor signal slew rate in several ways: the propagation delay of a signal with poor slew rate is increased and the propagation delay of the next stage in the circuit is also degraded by the slower switching rate at the input. The electrical integrity of the circuit is adversely effected since a poor slew rate at the input of a circuit is more susceptible to being effected by electrical noise which can come in the form of coupled line (or wire) noise or power supply noise.
What is required is a method for determining the factors which cause poor signal slew rates for each net on the chip and a method for determining what the best solution for improving the slew rate for each failing net is. Moreover, what is required is a way to automate the process and providing key information regarding the pertinent net characteristics and solution required to the chip designer and/or VLSI design system.
The invention solves the problem of exploring the tradeoffs of the solution space outlined above in an automated fashion and feeds back the solutions to the chip designer and VLSI design system.
The present invention is directed to a method, and a system for using the method, for automating a slew rate analysis between two or more functional elements on a semiconductor chip. The method includes the steps of: receiving as input one or more input parameters characterizing signals transmitted between the functional elements; and transmitting as output one or more output parameters characterizing the slew rates; and one or more output parameters characterizing a solution for slew rates not meeting a design target.
The receiving step can comprise any one of: providing a hierarchical signal name cross-reference defining a name for the signal for a given hierarchy level of the functional elements; providing a set of one or more boolean equations used to generate the one or more output parameters from the one or more input parameters; providing a physical design information for the functional elements; and providing a timing information for the signals.
The boolean equations permit a user to define the manner in which the transmitting step is performed. The boolean equations can include as input variables: the physical design information for the functional elements; and the timing information for the signals.
The step of providing physical design information for the functional elements includes any one of: determining the number of receiving circuits for the signal; determining the total length of all wires comprising the signal; determining the number of bits comprising the signal, if the signal comprises a bit in a communication bus; and determining the ratio of a first minimum distance through which the signal passes, wherein the first minimum distance includes intermediate pins through one or more of the functional elements, to a second minimum distance through which the signal passes, wherein the second distance lacks the intermediate pins.
The step of providing timing information for a signal comprises any one of: determining a slew for the signal at the driving end (near end); determining a slew for the signal at each receiving end (far end); determining a delay slack for the signal; determining an effective capacitance value for the signal as seen by the circuit driving the signal; determining an effective resistance value for the signal as seen by the circuit driving the signal; determining a total gate capacitance value of all circuits receiving the signal; and determining one or more parameters of a reduced standard parasitic format (RSPF) design tool.
The step of determining one or more parameters of an RSPF design tool comprises any one of: determining a second resistance value for the tool; determining a first capacitance value for the tool; determining a second capacitance value for the tool; and determining a third capacitance value for the tool.
FIGS. 1A-1C illustrate how RSPF models a wire. FIG. 1A illustrates a wire disposed between a driving circuit and a receiving circuit. FIG. 1B illustrates the model of this wire, as a pair of resistors R1, R2, a pair of capacitors C1 (with voltage drop Vc), C2, driven by the driving circuit. FIG. 1C illustrates a normalized version of the model of FIG. 1B, having Vc as a voltage source, resistor R3 normalized to the value of 1, an effective capacitance labeled C3, and the above-noted receiving circuit. Since R3 is normalized to 1, the xe2x80x9cRCxe2x80x9d time constant for the circuit is equivalent to R3C3, which is equivalent to C3.
The transmitting step can include the steps of: determining if a signal requires one or more buffers; determining if signal pin locations of the functional elements through hierarchical levels thereof are not optimal; determining if strengths of the circuit driving the signal must be increased; determining if the widths of wires used to transmit the signal must be increased; and determining if wires used to transmit the signal must be on less resistive wiring layers.